CLR70000 1.0 (0.8 L eff) CMOS Gate Arrays DS3697 ISSUE 2.0 March 1993 Ordering Information Features * 1.0 (0.8 Leff) twin well, epitaxial CMOS process * Architecture optimised for Quad Flat Packs * New peripheral design employing state-of-the-art pad pitch Photograph of Bonding Trials on CLR70000 General Description Advances in process geometry have resulted in denser and denser core logic. As a consequence the Industries `pad to gate' ratio (total number of pads vs number of available gates) has been reducing and the number of pad limited designs is rapidly increasing. The CLR70000 employs a completely new design of peripheral cell which is based on a state-of-the-art pad pitch allowing more pads per silicon area. The architecture of the arrays has been optimised to suit the popular JEDEC/EIAJ compliant QFP package types. Couple this with the proven CLA70000 0.8 (Leff) CMOS core and it's associated libraries and the CLR70000 is well positioned to combat todays fast growing QFP and `pad limited' CMOS Gate Array applications. * 12K to 54K available gates on a channelless array architecture * Low power consumption (<5W/gate/MHz) * Programmable slew controlled outputs. * 24mA drive capability * ESD protection in excess of 2kV * Fully compatible with CLA70000's extensive and proven core libraries. * Supports JTAG/BIST test philosophies (IEEE 1149-1 Test Procedures) * Design libraries available on Industry Standard workstations CLR70000 Family ARRAY RAW GATES PADS PACKAGE CLR73000 12200 104 MQFP100 FQFP100 TQFP100 CLR74000 19100 128 MQFP120 MQFP128 CLR75000 30900 160 MQFP144 TQFP144 MQFP160 CLR76000 53900 208 FQFP208 CLR70000 CMOS PROCESS TECHNOLOGY The CLR70000 arrays are based on GEC Plessey Semiconductors well proven 0.8 CMOS process, manufactured at Zarlink Semiconductors' advanced , Class 10, six-inch wafer fabrication facility. The process is a twin well, self aligned oxide-isolated technology, with an effective channel length of 0.8 (1.0 drawn ), giving a low defect density, high reliability, and inherently low power dissipation. The process has excellent immunity to latch-up, and ESD, and exhibits stable performance characteristics. Figure 1 - VQ' Process Cross Section CORE CELL DESIGN VDD Supply Programmable contacts Horizontal Routing Channels on Metal 1 VSS Supply The CLR70000 core is totally compatible with the well proven CLA70000 core. A four transistor group (2 NMOS and 2 PMOS) (fig 2.) forms the basic cell of the core array. This array element is repeated in a regular fashion over the complete core area to give a homogeneous `Full Field' (sea of gates) array. This lends itself to hierarchical design, allowing prerouted user defined subcircuits to be repeated anywhere on the array. The core cell structure has been carefully designed to maximise the number of nets which may be routed through the cell. This enables optimal routing for both data flow and control signal distribution schemes thus giving very high overall utilisation figures. This feature is of particular benefit in designs using highly structured blocks such as memory or arithmetic functions. Vertical Routing Channels on Metal 2 Figure 2 - Core Cell Design showing Cell Transparency INPUT/OUTPUT BUFFER DESIGN INPUT The CLR70000 employs a new generation of I/O cell taking advantage of design and assembly advances and new innovative pad layout techniques. IB6 IB5 IB4 IB3 The peripheral cells are fully programmable as Input, Output, VDD or GND, and they are designed to offer several interfacing options, TTL and CMOS for example. The cells already contain input `pull-up' and `pull-down' resistors and Electro Static Discharge protection elements. Components for implementing Schmitt Triggers, TTL threshold detectors, tristate control, and flip-flops for signal re-timing are also included. A range of output buffers is available with various output drive currents to match system requirements. IB2 IB1 Noise transients due to a large number of simultaneously switching outputs are an increasing problem as bus widths widen (The supply pad location, inductance of the bond wires and package leads are also factors). CLR70000 Arrays offer several I/O buffers with the capability to control the output slew (di/dt) which are invaluable in controlling these transients when driving large capacitive loads such as busses. Bonding Pad OUTPUT Figure 3 - CLR70000 Peripheral Cell Slew-controlled driver INPUT DATA P D N P OPT3 N PIN 50pF Delay 2.5V 2.5V Driver IB2BD IBSK1 IBSK2 IBSK3 Delay(nsec) 2.57 3.81 4.90 6.72 Current Ramp (mA/nSec) 107.30 47.40 22.90 11.00 Figure 4 - Slew Rate Control 2 CLR70000 CELL LIBRARIES Core Cells The CLR70000 array family employs the extensive CLA70000 core cell libraries developed from a broad range of ASIC experience over more than 15 years. Gate level and SSI functions are included in the MICROCELL Library, for implementation of `glue' logic and customer specific macros. To increase design productivity, the MACROCELL Library contains optimised SSI macro functions similar to standard TTL and CMOS logic families. A higher level of cells, particularly suitable for digital signal processing functions are to be found in the DSP MACROCELL Library. Memory cells (RAM and ROM) are individually generated within the PARACELL Library. To aid in testing of devices the BIST Library contains JTAG/IEEE-1149.1 elements facilitating Built-In-Self-Test methods such as scan path and signature analysis. More detailed information on all these libraries can be found in the CLA70000 datasheet, the CLA70000 design manual and the BIST application guide. PERIPHERAL CELLS INTERMEDIATE BUFFER CELLS Cell NPIBCMOS1 NPIBCMOS2 NPIBTTL1 NPIBBTL2 NPIBST1 NPIBST2 NPIBGATE NPIBCLKB NPIBDF NPIBDFA Description CMOS input buffer + large 2 input NAND gate CMOS input buffer + data latch TTL input buffer + large 2 input NAND gate TTL input buffer + data latch Input Schmitt buffer with CMOS switching levels Input Schmitt buffer with 2V switching levels NAND2/NOR2 gates Large clock driver Master-slave D type flip flop Master-slave D type flip flop Cell NPIBSK1 NPIBSK2 NPIBSK3 NPIBTRID NPIBTRID1 NPIBTRID2 NPIBTRID3 NPIB2BD NPDRV3 NPDRV6 Description Driver with slewed outputs Driver with slewed outputs Driver with slewed outputs Tri-state driver Tri-state driver with slewed outputs + 2 inverters Tri-state driver with slewed outputs + 2 inverters Tri-state driver with slewed outputs + 2 inverters Dual high powered inverters Clock driver Clock driver Cell NPOP1 NPOP2 NPOP3 NPOP6 NPOP12 NPOP5B NPOP11B NPOPT1 NPOPT2 NPOPT3 NPOPT6 NPOPT12 NPOP4TB NPOP10TB Description Smallest drive output cell Small drive output cell Standard drive output cell Medium drive output cell Large drive output cell Standard drive non-inverting output cell Large drive non-inverting output cell Smallest drive tri-state output cell Small drive tri-state output cell Standard drive tri-state output cell Medium drive tri-state output cell Large drive tri-state output cell Standard drive non-inverting tri-state output cell Large drive non-inverting tri-state output cell Cell NPIPNR NPIPR1P NPIPR1M NPIPR2P NPIPR2M NPIPR3P NPIPR3M NPIPR4P NPIPR4M Description Input cell with no pull up or down resistors Input cell with 1KOhm pull up resistor Input cell with 1KOhm pull down resistor Input cell with 2KOhm pull up resistor Input cell with 2KOhm pull down resistor Input cell with 4KOhm pull up resistor Input cell with 4KOhm pull down resistor Input cell with 100KOhm pull up resistor Input cell with 100K Ohm pull down resistor Cell NPOPVP NPOPVM NPIBVP NPIBVM NPLAVP NPLAVM NPIBLAVP Description VDD power cell for Outputs GND power cell for Outputs VDD power cell for Buffers GND power cell for Buffers VDD power cell for Logic Array GND power cell for Logic Array VDD power cell for Buffer and Logic Array Cell NPLAVDD NPLAGND NPIBLAVDD NPIBLAGND NPALLVP NPALLVM NPALLVDD Description VDD power cell for Logic Array GND power cell for Logic Array VDD power cell for Buffer and Logic Array GND power cell for Buffer and Logic Array VDD power cell for All rails GND power cell for All rails VDD power cell for All rails NPIBLAVM GND power cell for Buffer and Logic Array NPALLGND GND power cell for All rails OUTPUT CELLS Cell NPOPOD1 NPOPOD2 NPOPOD3 NPOPOD6 NPOPOD12 NPOPOD5B NPOPOD11B NPOPOS1 NPOPOS2 NPOPOS3 NPOPOS6 NPOPOS12 NPOPOS5B NPOPOS11B INPUT CELLS Description Smallest drive open-drain output cell Small drive open-drain output cell Standard drive open-drain output cell Medium drive open-drain output cell Large drive open-drain output cell Standard drive non-inverting open-drain output cell Large drive non-inverting open-drain output cell Smallest drive open-source output cell Small drive open-source output cell Standard drive open-source output cell Medium drive open-source output cell Large drive open-source output cell Standard drive non-inverting open-source output cell Large drive non-inverting open-source output cell OSCILLATOR CELLS * Cell Description NPOSC1 1 to 5MHz Crystal Oscillator NPOSC2 5 to 20MHz Crystal Oscillator NPOSC4 15 to 40MHz Crystal Oscillator NPLPOSC Low Power 32KHz Crystal Oscillator NPOSC1ENB 1 to 5MHz Crystal Oscillator with Pwr Down NPOSC2ENB 5 to 20MHz Crystal Oscillator with Pwr Down NPOSC3ENB 32KHz to 1MHz Crystal Osc. with Pwr Down NPOSC4ENB 15 to 40MHz Crystal Osc. with Pwr Down * In development, please confirm status with local Design Centre POWER SUPPLY CELLS Our Libraries are continually being enhanced, so please contact your local Design Centre for the latest information. 3 CLR70000 DC ELECTRICAL CHARACTERISTICS All characteristics at Commercial Grade voltage and temperature (0 - 70C, 4.5V -5.5V) CHARACTERISTIC SYM LOW LEVEL INPUT VOLTAGE TTL Inputs CMOS Inputs VALUE Typ Max VIL CONDITIONS 0.8 1.0 VIH (NPIBTTL1/NPIBTTL2) (NPIBCMOS1/NPIBCMOS2) INPUT HYSTERESIS (NPIBST1) Rising Falling (NPIBST2) Rising Falling UNIT V (NPIBTTL1/NPIBTTL2) (NPIBCMOS1/NPIBCMOS2) HIGH LEVEL INPUT VOLTAGE TTL Inputs CMOS Inputs Min V 2.0 VDD - 1.0 V VT+ VTVT+ VT- INPUT CURRENT/RESISTANCE (CMOS / TTL INPUTS) No Resistor Inputs with 1Kohm Resistors Inputs with 2Kohm Resistors Inputs with 4Kohm Resistors Inputs with 75Kohm Resistors 3.1 1.9 1.7 1.1 IIN -1 0.5 1 2 25 HIGH LEVEL OUTPUT VOLTAGE All outputs Smallest drive cell NPOP1/NPOPT1/NPOPOS1 Low drive cell NPOP2/NPOPT2/NPOPOS2 Standard drive cell NPOP3/NPOPT3/NPOPOS3 Medium drive cell NPOP6/NPOPT6/NPOPOS6 Large drive cell NPOP12/NPOPT12/NPOPOS12 VOH LOW LEVEL OUTPUT VOLTAGE All outputs Smallest drive cell NPOP1/NPOPT1/NPOPOD1 Low drive cell NPOP2/NPOPT2/NPOPOD2 Standard drive cell NPOP3/NPOPT3/NPOPOD3 Medium drive cell NPOP6/NPOPT6/NPOPOD6 Large drive cell NPOP12/NPOPT12/NPOPOD12 VOL TRISTATE OUTPUT LEAKAGE CURRENT All open drain output cells IOZ OUTPUT SHORT CIRCUIT CURRENT Standard outputs NPOP3/NPOPT3/NPOPOS3 (See note 1) NPOP3/NPOPT3/NPOPOD3 IOS +1 2 4 8 250 INPUT CAPACITANCE BIDIRECTIONAL PIN CAPACITANCE VIN = VDD or VSS V VDD - 1.0 VDD - 1.0 VDD - 1.0 VDD - 1.0 VDD - 1.0 IOH = -1A IOH = -2mA IOH = -4mA IOH = -6mA IOH = -12mA IOH = -24mA V VDD + 0.05 0.2 0.2 0.2 0.2 0.2 IOL = 1A IOL = 2mA IOL = 4mA IOL = 6mA IOL = 12mA IOL = 24mA 0.4 0.4 0.4 0.4 0.4 A 1 VOH = VSS or VDD mA 21 54 IDDOP 45 102 75 165 VDD = MAX, VOUT = GND VDD = MAX, VOUT = VDD A/MHz 1 CI OUTPUT CAPACITANCE A K K K K VDD - 0.05 VDD - 0.5 VDD - 0.5 VDD - 0.5 VDD - 0.5 VDD - 0.5 -1 OPERATING SUPPLY CURRENT (per gate) (see note 2) VIL to VIH VIH to VIL VIL to VIH VIH to VIL 5 pF ANY INPUTS (see note 3) COUT 5 pF ANY OUTPUT (see note 3) CVO 7 pF ANY I/O PIN (see note 4) Note 1: Standard driver output NPOP3 etc. Short circuit current for other outputs will scale. Not more than one output may be shorted at a time for a maximum duration of one second. Note 2: Excluding peripheral buffers. Note 3: Excludes package leadframe capacitance or bidirectional pins. Note 4: Excludes package. ABSOLUTE MAXIMUM RATINGS PARAMETER MIN MAX UNITS Supply Input Output Voltage Voltage Voltage - 0.5 - 0.5 - 0.5 7.0 VDD+0.5 VDD+0.5 RECOMMENDED OPERATING LIMITS V V V Operation above these absolute maximum ratings or prolonged periods above the recommended operating limits may permanently damage device characteristics and may affect reliability. Storage Temperature: Plastic - 40 4 125 degree C PARAMETER MIN MAX Supply Voltage Input Voltage Output Voltage Current per pad 3.0 VSS VSS 5.5 VDD VDD 100 V V V mA 70 85 degree C degree C Operating Temperature: Commercial Grade 0 Industrial Grade -40 UNITS CLR70000 DESIGN TOOLS The focus of the GEC Plessey design tool methodology is that of maintaining an open CAD system with all interfaces standardized via EDIF 2.0 . This enables us to provide full support for a variety of 3rd party ASIC design tools and facilitates rapid updating of associated libraries. It also provides an interface to the GEC Plessey (PDS2) design system, which offers a total design environment including behavioral and functional level modelling. PDS2 - THE ZARLINK SEMICONDUCTOR ASIC DESIGN SYSTEM * Behavioral, Functional, and Gate Level Modelling * VHDL and Third Party Links * Supports Hierarchical Design Techniques * EDIF 2.0 Interface PDS2 is Zarlink Semiconductors own proprietary ASIC design system. It provides a fully-integrated, technology independent VLSI design environment for all Zarlink Semiconductors CMOS SemiCustom products. PDS2 runs on Digital Equipment Corporation computers and is self configuring according to the available machine resources. It comprises design capture (schematic capture or VHDL), testability analysis, logic simulation, fault simulation, auto place and route, and back annotation. The system offers full support for hierarchical design techniques, maintained from design capture through to layout, as well as advanced design management tools. PDS2 may be used either at a Zarlink Semiconductors Design Centre or under licence at the customer's premises. A three day training course is available for first time users. THIRD PARTY SOFTWARE SUPPORT * Design Kits for major industry standard ASIC design software tools * All libraries include fully detailed timing information * EDIF 2.0 Interface * Post layout back annotation available Zarlink Semiconductor supports a wide range of third party design tools including IKOS, Mentor, Verilog, and Viewlogic. The design kits offer fully detailed timing information for all cell libraries, netlist extraction utilities, and post layout back annotation capability where applicable. An example of a workstation design flow is shown in the figure 5 (opposite). Please contact your local GEC Plessey Semiconductor's sales office for further information about support of particular tools. DESIGN SUPPORT Design support is available from various centres worldwide each of which is connected to our Headquarters via high speed data links. A design centre engineer is assigned to each customers circuit, to ensure good communication, and a smooth and efficient design flow. As part of the design process arlink Semiconductor operates a thorough design audit procedure to verify compliance with customer specification and to ensure manufacturability. The procedure includes four separate review meetings, with the customer, held at key stages of the design. The standard design audit procedure is outlined opposite. PDS ENVIRONMENT WORKSTATION ENVIRONMENT Schematic Capture Schematic Symbols CLA Libraries ERC & Netlist Translation Back Annotation Simulation Models Simulation Test Vector Generation MLE Place & Route Design Verification Vector Translation Test Program Generation Figure 5 - Workstation Design Flow Review 1: Review 2 Review 3 Review 4 Held at the beginning of the design cycle to check and agree on specifications and design timescales. Held after Logic Simulation and prior to Layout. Checks to ensure satisfactory functionality, timing performance, and adequate fault coverage Held after Layout and Post layout Simulation. Verification of design performance after insertion of actual track loads. Final check of all device specifications before prototype manufacture. Held after prototype delivery. Confirms that the devices meet the specification and are suitable for full scale production. 5 http://www.zarlink.com World Headquarters - Canada Tel: +1 (613) 592 0200 Fax: +1 (613) 592 1010 North America - West Coast Tel: (858) 675-3400 Fax: (858) 675-3450 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 North America - East Coast Tel: (978) 322-4800 Fax: (978) 322-4888 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. 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No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink Semiconductor's conditions of sale which are available on request. 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